Systems, methods, and apparatus for supporting multiple connectors on storage devices

ABSTRACT

A storage device may include a connector comprising a power management pin, a detector circuit configured to detect a transition of a power management signal received on the power management pin, and a power management circuit capable of configuring power to at least a portion of the storage device based, at least in part, on the detector circuit detecting a transition of the power management signal. The connector may further include a port enable pin, and the power management circuit may be configured to be disabled based, at least in part, on a state of the port enable pin. A storage device may include a connector comprising a power management pin, a nonvolatile memory, and a power management circuit configured to operate in a first power management mode based on determining a first state of the nonvolatile memory.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.16/926,636, filed on Jul. 10, 2020, which claims priority to, and thebenefit of, U.S. Provisional Patent Application Ser. No. 63/010,041,filed on Apr. 14, 2020 which are both incorporated by reference.

TECHNICAL FIELD

This disclosure relates generally to storage devices, and morespecifically to systems, methods, and apparatus for supporting multipleconnectors on storage devices.

BACKGROUND

A storage device may be coupled to a host system through a connector. Aconnector may include a power management pin that may cause the storagedevice to configure power in response to a power management signalapplied to the power management pin.

The above information disclosed in this Background section is only forenhancement of understanding of the background of the invention andtherefore it may contain information that does not constitute prior art.

SUMMARY

A storage device may include a connector comprising a power managementpin, a detector circuit configured to detect a transition of a powermanagement signal received on the power management pin, and a powermanagement circuit capable of configuring power to at least a portion ofthe storage device based, at least in part, on the detector circuitdetecting a transition of the power management signal. The connector mayfurther include a dual port enable pin, and the power management circuitmay be configured to be disabled based, at least in part, on a state ofthe dual port enable pin. The storage device may further include anonvolatile memory, and the power management circuit may be configuredto be disabled or enabled, for example, by firmware, at least in part,on a state of the nonvolatile memory. The detector circuit may beconfigured to latch the power management pin based, at least in part, onthe state of the nonvolatile memory. The power management pin mayinclude a power disable pin, and the power management circuit may becapable of disabling power to at least a portion of the storage devicebased on the detector circuit detecting a transition of the powermanagement signal.

A storage device may include a connector comprising a power managementpin, a nonvolatile memory, and a power management circuit configured tooperate in a first power management mode based on determining a firststate of the nonvolatile memory. In the first power management mode, thepower management circuit may configure power to at least a portion ofthe storage device based, at least in part, on a power management signalreceived on the power management pin. The storage device may furtherinclude a detector circuit configured to detect a transition of a powermanagement signal received on the power management pin, and the powermanagement circuit may disable power to at least a portion of thestorage device based, at least in part, on the detector circuitdetecting a transition of the power management signal. The connector mayfurther include a dual port enable pin, and the power management circuitis configured to disable at least a portion of the storage device based,at least in part, on a state of the dual port enable pin. The storagedevice may be configured as a U.3 storage device in the first powermanagement mode. The power management pin may include a power disablepin. The power management circuit may be configured to operate in asecond power management mode based on determining a second state of thenonvolatile memory. In the second power management mode, the powermanagement circuit may disable power to at least a portion of thestorage device. The storage device may be configured as a U.2 storagedevice in the second power management mode.

A method may include coupling a storage device to a host through aconnector, detecting a transition of a power management signal receivedfrom the host at the storage device through the connector, andconfiguring power to at least a portion of the storage device based, atleast in part, on detecting the transition on the power managementsignal. Configuring power to at least a portion of the storage devicemay include disabling power to at least a portion of the storage device.The power to the at least a portion of the storage device may beconfigured based, at least in part, on the state of a nonvolatilememory. The method may further comprise latching the power managementsignal based on a reset signal. The power to the at least a portion ofthe storage device may be configured based, at least in part, on thestate of a dual port enable signal received from the host at the storagedevice through the connector. The method may further include latchingthe dual port enable signal based on a reset signal.

BRIEF DESCRIPTION OF THE DRAWINGS

The figures are not necessarily drawn to scale and elements of similarstructures or functions are generally represented by like referencenumerals for illustrative purposes throughout the figures. The figuresare only intended to facilitate the description of the variousembodiments described herein. The figures do not describe every aspectof the teachings disclosed herein and do not limit the scope of theclaims. To prevent the drawing from becoming obscured, not all of thecomponents, connections, and the like may be shown, and not all of thecomponents may have reference numbers. However, patterns of componentconfigurations may be readily apparent from the drawings. Theaccompanying drawings, together with the specification, illustrateexample embodiments of the present disclosure, and, together with thedescription, serve to explain the principles of the present disclosure.

FIG. 1 illustrates an example embodiment of a storage device having adetector circuit according to this disclosure.

FIG. 2 illustrates an example embodiment of a storage device havingconfigurable power management according to this disclosure.

FIG. 3 illustrates a truth table for an example embodiment of a storagedevice having transition detection and configurable power managementaccording to this disclosure.

FIG. 4 illustrates an example embodiment of a detector circuit for apower disable signal for a storage device according to this disclosure.

FIG. 5 illustrates another example embodiment of a detector circuit fora power disable signal for a storage device according to thisdisclosure.

FIG. 6 illustrates an embodiment of a sampling circuit that may be used,for example, to generate a dual port enable valid signal according tothis disclosure.

FIG. 7 illustrates a timing diagram of an example embodiment of a methodfor generating a dual port enable valid signal according to thisdisclosure.

FIG. 8 illustrates a timing diagram of an example embodiment of a methodtiming for sampling a power disable signal according to this disclosure.

FIG. 9 illustrates an embodiment of a method for managing power in astorage device according to this disclosure.

DETAILED DESCRIPTION

In some embodiments, a storage device may manage power within the devicein response to detecting a transition on a power management signalreceived through a connector from the host. In some embodiments,detecting a transition on a power management signal may enable a storagedevice to be compatible with different host connectors having differentpin definitions that may otherwise be incompatible. For example, a firsthost connector may have a power disable pin defined as an active lowsignal. A second host connector may use the same (or mechanicallycompatible) connector, but define the same power disable pin as anactive high signal. This may cause a storage device designed for thesecond host connector to behave incorrectly (e.g., enter a power disablestate) when plugged into the first host connector.

However, in some implementations of the first host connector, the powerdisable pin may always be pulled to the high state (e.g., it may nothave any transitions), while in some implementations of the second hostconnector, the power disable signal is an active high and may havetransitions from low to high states. Thus, by detecting a transition ofthe power disable signal, a storage device may distinguish between avalid power disable event on the second host connector, and the absenceof a power disable event on the first host connector.

In some embodiments, a power management feature of a storage device maybe configured in response to the state of a nonvolatile memory. Forexample, a storage device may have a power management circuit that mayenable or disable power to at least a portion of the storage device inresponse to the state of a configuration bit in nonvolatile memory. Insome embodiments, such a configurable power management feature mayenable a single storage device to be programmed or configured, forexample, for use with different types of host connectors.

The features described in this disclosure may have independent utilityand may be embodied individually, and not every embodiment may utilizeevery feature. Moreover, the features may also be embodied in variouscombinations, some of which may amplify the benefits of the individualprinciples in a synergistic manner.

Some example embodiments of systems, processes, methods, and/or the likeillustrating some possible implementation details according to thisdisclosure are described below. These examples are provided for purposesof illustrating the principles of this disclosure, but the principlesare not limited to these embodiments, implementation details, and/or thelike.

FIG. 1 illustrates an example embodiment of a storage device having adetector circuit according to this disclosure. The storage device 100illustrated in FIG. 1 may include a connector 102, a detector circuit104, a power management circuit 106, a storage device controller 108,and a storage media 110. The connector 102 may include a powermanagement pin 112.

The connector 102 may be implemented with any type of standard ornon-standard connector that may be used to connect a storage device to ahost. Some examples may include connectors described in the SFF-8639specification such as those known as U.2 and/or U.3 (SFF-TA-1001specification) connectors, scalable connectors such as those describedin the SFF-TA-1002 specification, M.2 connectors, any connectors thatmay be used with any storage interconnects such as those used withSerial Advanced Technology Attachment (SATA), Small Computer SystemsInterface (SCSI), and/or Serial Attached SCSI (SAS), and/or the like,and/or any other connectors having any mechanical and/or electricalconfiguration and/or any configuration of pins.

The detector circuit 104 may be implemented with any analog and/ordigital hardware, software, and/or any combination thereof, that maydetect a transition in a power management signal received on the powermanagement pin 112 as mentioned above. For example, in some embodimentsin which the connector may be implemented as a U.3 connector, thedetector circuit 104 may detect a low-to-high transition of the PWRDISsignal on pin P3 of the connector to recognize a valid power disableevent as described in more detail below.

The power management circuit 106 may be implemented with any analogand/or digital hardware, software, and/or any combination thereof thatmay, for example, enable and/or disable or reduce power to all or anyportions of the storage device 100. For example, the power managementcircuit 106 may include various power distribution and/or conditioningcircuitry to receive power from a host through various additional pinsof the connector 102 and distribute it throughout the storage device100.

The storage medium 110 may be implemented with magnetic, solid state,optical, and/or any other type of data storage technology or combinationthereof. Thus, the storage device 100 may be implemented as hard diskdrive (HDD), a solid state drive (SSD), an optical disk drive (ODD),and/or any other type of storage device.

The storage device controller 108 may be implemented with any hardware,software, and/or any combination thereof that may control the storageand other functions of the storage device 100. For example, in someembodiments that may use flash memory such as Not-AND (NAND) memory asthe storage media 110, the storage device controller 108 may include aflash translation layer (FTL).

The storage device 100 may include additional components and/orsubcomponents and/or interconnections therebetween, not illustrated inFIG. 1 . For example, some embodiments may include one or morecommunication interfaces, for example, network interfaces such asEthernet, Fibre Channel, InfiniBand, and/or the like, storage or otherinterconnects and/or protocols such as Peripheral Component InterfaceExpress (PCIe), SAS, SATA, Nonvolatile Memory Express (NVMe), NVMe OverFabric (NVMe-oF), and/or the like, to interface the storage devicecontroller and/or other components to various pins of the connector 102.As another example, some embodiments may include one or morecomputational components such as field programmable gate arrays (FPGAs),embedded graphics processing units (GPUs), and/or the like.

Although some components may be illustrated as individual components inFIG. 1 , some or all of the components may be integrated into, and/ordistributed between, other components.

FIG. 2 illustrates an example embodiment of a storage device havingconfigurable power management according to this disclosure. The storagedevice 114 illustrated in FIG. 2 may include some components similar tothose in the embodiment illustrated in FIG. 1 such as a connector 102having a power management pin 112, a power management circuit 106, astorage device controller 108, and a storage media 110. However, thestorage device 114 illustrated in FIG. 2 may also include a nonvolatilememory (NVM) 116 which may be used to configure and/or reconfigure anypower management features of the storage device 114. For example, insome embodiments, the NVM 116 may be used to control the powermanagement circuit 106 to enable or disable power to all or one or moreportions of the storage device.

The NVM 116 may be implemented with any technique that may save the modeor configuration of any power management features of the storage device114. Some examples may include one or more bits of read only memory(ROM), programmable read only memory (PROM), battery-backed randomaccess memory (RAM), and/or flash memory, and/or the like. Someadditional examples may include one or more fuses, cut traces, jumpers,dipswitches, headers, wires inserted or removed from a circuit board,and/or the like.

In some embodiments, and depending on the implementation details,configuring a power management feature based on a nonvolatile memory mayenable a storage device to be configured and/or reconfigured anywherealong the supply chain, for example, by a manufacturer, distributor,user, and/or the like. For example, if the NVM is implemented with oneor more bits of electrically reprogrammable memory such as flash memory,a manufacturer, distributor, user, and/or the like may reprogram thepower management configuration of the storage device by accessing theflash memory through any technique such as, for example, a firmwareupdate utility. Moreover, having configurable power management mayimprove economies of scale by enable a manufacturer to fabricate moredevices of a single design and program them as different types ofdevices.

FIG. 3 illustrates a truth table for an example embodiment of a storagedevice having signal transition detection and configurable powermanagement according to this disclosure. The embodiment illustrated withrespect to FIG. 3 may be described in the context of storage devicesthat may be configured to enable a U.3 storage device to be used with ahost having a U.2 connector, but the inventive principles are notlimited to these example details.

In some embodiments, a U.2 host connector may be configured for use withthe SATA Express specification which may define pin P3 of the connectoras an active low clock request signal (CLKREQ #). When asserted (low),the CLKREQ # signal may cause a storage device plugged into theconnector to enter a power disable state. In some embodiments, pin P3 ofa UI host connector may be permanently pulled to a high logic level bythe host to prevent a U.2 storage device plugged into the U.2 hostconnector from entering a power disable state. In some embodiments, pinP3 of a U.2 host connector may be pulled to a high logic level for ahost that may be non SATA based (e.g., SAS or NVMe based) to disable thepower disable feature by default.

In some embodiments, a U.3 host connector may be configured with pin P3of the connector defined as an active high power disable signal(PWRDIS). Thus, if a U.3 storage device is plugged into a U.2 hostconnector, it may operate incorrectly by entering a power disable statein response to a high logic level on pin P3 of the connector. Thus,separate U.2 and U.3 storage devices may be used to provide correctoperation with U.2 and U.3 host connectors. In some embodiments, anddepending on the implementation details, this may increase the number ofdevice types that a manufacturer, distributor, user, and/or the like mayneed to manufacture, stock, and/or the like.

Moreover, in some embodiments, a dual port feature of a storage devicemay further complicate the implementation of a power management feature.For example, in some embodiments, a power disable or other powermanagement feature may be disabled when a storage device is configuredfor dual port operation. The power management may be disabled, forexample, because dual port operation may be part of a high availabilityconfiguration which, in some implementations, may be inconsistent with apower disable state. Thus, having dual port enabled versions of each ofthe U.2 and/or U.3 versions of storage devices may further increase thenumber of device types that a manufacturer, distributor, user, and/orthe like may need to manufacture, stock, and/or the like.

In some embodiments, and depending on the implementation details, astorage device having signal transition detection and configurable powermanagement according to this disclosure may enable a single storagedevice to operate correctly in both U.2 and U.3 host connectors, whilealso enabling single port and dual port configurations with the samedevice.

For example, to implement the features illustrated in FIG. 3 , anembodiment of a storage device may implement a detector circuit todetect a transition in the PWRDIS signal on pin P3 of a U.3 connector asshown in the embodiment illustrated in FIG. 1 . Such an embodiment mayalso enable or disable a power disable circuit based on the programmedstate of an NVM cell as shown in the embodiment illustrated in FIG. 2 .

Referring again to FIG. 3 , an embodiment of a storage device mayoperate as shown in the column labeled “operation” in response to thestate of pin P3 and pin E25 depending on the programmed state of an NVMcell. Specifically, the NVM cell may be programmed to a first state toconfigure the storage device as a U.2 storage device. Alternatively, theNVM cell may be programmed to a second state to configure the storagedevice as a U.3 storage device. Pin E25 may be defined as an active lowdual port enable signal (DualPortEn #) for both U.2 and U.3 deviceconnectors and host connectors. Pin P3 may be defined as an active lowclock request signal (CLKREQ #) when the storage device is configured asa U.2 device, and an active high power disable signal (PWRDIS) when thestorage device is configured as a U.3 device.

Referring to the second row of FIG. 3 in which both of pins P3(PWRDIS/CLKREQ #) and E25 (DualPortEn #) are low, the storage device mayoperate in dual port mode with power management disabled, regardless ofwhether the device is configured as a U.2 or U.3 device by the NVM cell.In some embodiments that may not be SATA based (e.g., SAS and/or NVMebased), the state of the NVM cell may be ignored, for example, becauseit may not be applicable. In some implementations, the pin P3 may besampled during a low-to-high transition of a PCIe reset signal (PERST#).

Referring the third row of FIG. 3 in which pin P3 (PWRDIS/CLKREQ #) islow and E25 (DualPortEn #) is high, the storage device may operate insingle port mode with power management disabled, regardless of whetherthe device is configured as a U.2 or U.3 connector by the NVM cell.

Referring to the fourth row of FIG. 3 in which pin P3 (PWRDIS/CLKREQ #)is high and E25 (DualPortEn #) is low, the storage device may operate indual port mode with power management disabled, regardless of whether thedevice is configured as a U.2 or U.3 connector by the NVM cell.

Referring to the fifth row of FIG. 3 in which both of pins P3(PWRDIS/CLKREQ #) and E25 (DualPortEn #) are high, the storage devicemay operate in single port mode regardless of whether the device isconfigured as a U.2 or U.3 device by the NVM cell. If the device isconfigured as a U.2 device, power management may be disabled. However,if the device is configured as a U.3 device, power management may beenabled, and the device may enter a power disable state in response todetecting a low-to-high transition of the PWRDIS signal.

Thus, in some embodiments, and depending on the implementation details,a storage device operating as illustrated in FIG. 3 may implementcorrect operation as a U.3 storage device when plugged into a U.3 hostconnector (e.g., proper implementation of power management in responseto the PWRDIS signal), while still remaining operational (not entering apower disable state) when plugged into a U.2 host connector.

FIG. 4 illustrates an example embodiment of a detector circuit for apower disable signal for a storage device according to this disclosure.The circuit 120 illustrated in FIG. 4 may include an input terminal 122to receive a power disable input signal (PWRDIS) which may be filteredby a filter circuit including resistors R1, R2 and capacitor C1. ThePWRDIS signal may be received, for example, from a power management pinon a connector (e.g., pin P3 on a U.3 connector). The filtered inputsignal VD_IN may pass through a complex programmable logic device (CPLD)124 and be applied as VD_OUT to one input of a 3-input AND gate 126. Theoutput of the AND gate may be applied to the G input of a D flip-flop128, which may provide an output power enable signal (CHIP_EN). A powermanagement enable/GPIO signal (Power Management Enable) may be appliedto a second input of the 3-input AND gate 126, and a dual port enablevalid signal (DualPortEN_Valid) may be applied to the third input of the3-input AND gate 126.

In some embodiments, the input terminal 122, filter circuit, CPLD 124and D flip-flop 128 may be part of an existing circuit in a storagedevice, for example, as part of the storage device controller 108illustrated in FIG. 1 . Thus, the detector circuit 120 illustrated inFIG. 4 may take the existing signal VD_OUT and qualify it with a powermanagement enable signal and a dual port enable signal before it islatched by the flip-flop 128.

The CHIP_EN signal may disable power to all or some portions of thestorage device. For example, the CHIP_EN signal may be applied as a gatesignal to a power management circuit that may receive power from a hostthrough pins of a connector and distribute it throughout the storagedevice.

The Power Management Enable signal may be generated, for example, byfirmware in a storage device based on reading the state of aconfiguration bit in a register in NVM. Thus, in some embodiments, thePower Management Enable signal may enable the circuit 120 to be used toconfigure a storage device as a U.2 device or a U.3 device, for example,as illustrated in FIG. 3 .

The DualPortEN_Valid signal may be generated, for example, by readingthe state of a dual port enable pin on a connector (e.g., pin E25 on aU.3 connector), either directly or through an inverter. Alternatively,The DualPortEN_Valid signal may be generated, for example, by latchingthe state of a dual port enable pin on a connector in response to areset signal as described in more detail below.

Thus, in some embodiments, the DualPortEN_Valid signal may provide asingle port indication to the power management circuit which may be usedto qualify pin P3 only if the storage device is in a single portconfiguration. In a dual port configuration, pin P3 may be ignored, forexample, as illustrated in FIG. 3 . As described with respect to FIG. 3, in some embodiments, a power disable feature may only be used for asingle port configuration. For a dual port configuration, power disablemay not be support, for example, because power disable may beinconsistent with high availability operation. Thus, in someembodiments, the AND gate 126 may only enable the PWRDIS signal to belatched by the flip-flop 128 when the storage device is operating insingle port configuration.

FIG. 5 illustrates another example embodiment of a detector circuit fora power disable signal for a storage device according to thisdisclosure. The circuit 130 illustrated in FIG. 5 may include somecomponents similar to those in the embodiment illustrated in FIG. 4 .However, in the embodiment illustrated in FIG. 5 , the AND gate 132 maybe implemented as a 2-input AND gate, and the Power Management Enablesignal may instead be applied to the D input of a D flip-flop 134 in theCPLD 136 through resistor R3. In this embodiment, the PWRDIS signal maybe applied as the clock input to the flip-flop 134. Thus, the state ofthe Power Management Enable signal may be latched on a low-to-hightransition of the PWRDIS signal, which may enable the circuit 130 todetect the low-to-high transition of the PWRDIS signal, which may beused to enter a power disable state, but qualified by the state of thePower Management Enable signal. Thus, when implemented in a U.3 storagedevice, the circuit 130 may enable the storage device to correctlydetermine that it is connected to a U.3 host connector, and therefore,to determine that high logic level on the PWRDIS pin signals a validpower disable event, as opposed to a constant high logic level on a U.2host connector.

In some embodiments, and depending on the implementation details, eitherof the detector circuits 120 and/or 130 may be implemented, for example,as a dangle or add-on board which may be attached to an existing circuitboard for a storage device. Thus, in some embodiments, an existingstorage device may be converted to provide power managementreconfiguration and/or correct power disable and/or dual port operationwith relatively low impact on a manufacturing and/or modificationoperation. Moreover, in some embodiments, and depending on theimplementation details, either of the detector circuits 120 and/or 130may be integrated into new designs with little or no increase in costs,development time, and/or the like.

FIG. 6 illustrates an embodiment of a sampling circuit that may be used,for example, to generate a dual port enable valid signal according tothis disclosure. The circuit 140 illustrated in FIG. 6 may include aninput terminal 142 to receive an active low PCIe reset signal PERST #,for example from a pin of a connector. After being filtered by a filtercircuit including resistor R4, R5 and capacitor C2, the PERST # signalmay be applied to the clock input of a D flip-flop 144 in a CPLD 146. Adual port enable signal (DualPortEN #), for example, from a dual portenable pin on a connector (e.g., pin E25 on a U.2 or U.3 connector) maybe applied as the D input to the flip-flop 144 through resistor R6.Thus, an active low DualPortEN #_Valid signal may be generated bylatching the DualPortEN # signal in response to a low-to-high transitionof the PERST # signal. A complementary DualPortEN_Valid signal may beprovided through an inverter 148.

FIG. 7 illustrates a timing diagram of an example embodiment of a methodfor generating a dual port enable valid signal according to thisdisclosure. The method illustrated in FIG. 7 may be used for example, atpower-up with the sampling circuit illustrated in FIG. 6 . Referring toFIG. 7 , by time t1, one or more power supply rails may be stabilize,and the DualPortEN # signal may be valid. The state of the DualPortEN #signal may be latched at time t2 in response to activation of the activelow PCIe reset signal PERST #. The time period T1 between times t1 andt2 may be specified, for example, based on a hold time for theDualPortEN # signal, a minimum time after the one or more power supplyrails may be within a specified tolerance, and/or the like.

In some embodiments, a power management signal, for example, a powerdisable signal such as PWRDIS, may be latched in response to a resetsignal such as a PCIe reset signal PERST #. In some embodiments, a powermanagement signal may be latched using a sampling circuit similar tocircuit 140 used for the dual port enable valid signal as shown in FIG.6 .

FIG. 8 illustrates a timing diagram of an example embodiment of a methodtiming for sampling a power disable signal according to this disclosure.The method may begin with an active high power disable signal PWRDIS ata low logic level and a PCIe reset signal PERST # in an indeterminatestate. The PWRDIS signal may be driven to an active high state at timet1 and held in the active high state for a time period Tpwrdis untiltime t2 when the PWRDIS signal may be deactivated to the low state. ThePERST # signal may be driven to an active low state at some point beforethe PWRDIS is deactivated at time t2. The PERST # signal may then bedeactivated at time t3, which may occur after a hold time Tdisrst afterthe PWRDIS signal is deactivated at time t2.

The embodiments illustrated in FIGS. 6-8 may be beneficial for example,for providing defined and/or determinate behavior, and/or for purposesof compliance with specifications with embodiments of storage devicesthat may be used with scalable connectors such as those described in theSFF-TA-1002 specification and using signals as defined, for example, inthe STT-TA-1009 specification.

FIG. 9 illustrates an embodiment of a method for managing power in astorage device according to this disclosure. The method may begin atoperation 150 by coupling a storage device to a host through aconnector. At operation 152 the method may detect a transition of apower management signal received from the host at the storage devicethrough the connector. At operation 154, the method may configure powerto at least a portion of the storage device based, at least in part, ondetecting the transition on the power management signal.

The operations and/or components described with respect to theembodiment illustrated in FIG. 9 , as well as any other embodimentsdescribed herein, are example operations and/or components. In someembodiments, some operations and/or components may be omitted and/orother operations and/or components may be included. Moreover, in someembodiments, the temporal and/or spatial order of the operations and/orcomponents may be varied.

The embodiments disclosed above have been described in the context ofvarious implementation details, but the principles of this disclosureare not limited these or any other specific details. For example, somefunctionality has been described as being implemented by certaincomponents, but in other embodiments, the functionality may bedistributed between different systems and components in differentlocations and having various user interfaces. Certain embodiments havebeen described as having specific processes, steps, etc., but theseterms also encompass embodiments in which a specific process, step, etc.may be implemented with multiple processes, steps, etc., or in whichmultiple process, steps, etc. may be integrated into a single process,step, etc. A reference to a component or element may refer to only aportion of the component or element. For example, a reference to anintegrated circuit may refer to all or only a portion of the integratedcircuit, and a reference to a block may refer to the entire block or oneor more subblocks. The use of terms such as “first” and “second” in thisdisclosure and the claims may only be for purposes of distinguishing thethings they modify and may not to indicate any spatial or temporal orderunless apparent otherwise from context. In some embodiments, “based on”may refer to “based at least in part on.” In some embodiments,“disabled” may refer to “disabled at least in part.” A reference to afirst thing may not imply the existence of a second thing.

The various details and embodiments described above may be combined toproduce additional embodiments according to the inventive principles ofthis patent disclosure. Since the inventive principles of this patentdisclosure may be modified in arrangement and detail without departingfrom the inventive concepts, such changes and modifications areconsidered to fall within the scope of the following claims.

1. A storage device comprising: a connector comprising a powermanagement pin; a detector circuit configured to detect a valid a powermanagement signal received on the power management pin; and a powermanagement circuit capable of configuring power to at least a portion ofthe storage device based, at least in part, on the detector circuitdetecting a valid power management signal.